Resolving double patterning conflicts

ABSTRACT

A mechanism is provided for resolving patterning conflicts. The mechanism performs decomposition with stitches at all candidate locations to find the solution with the minimum number of conflicts. The mechanism then defines interactions between a layout of a first mask and a layout of a second mask through design rules, as well as interactions of mask 1 /mask 2  with top and bottom layers (i.e., contacts, vial, etc.). The mechanism then gives the decomposed layout and design rule definition to any existing design rule fixing or layout compaction tool to solve native conflicts. The modified design rules are that same-layer spacing equals spacing of single patterning, different-layer spacing equals spacing of final layout, and layer overlap equals minimum overlap length.

BACKGROUND

The present application relates generally to an improved data processingapparatus and method and more specifically to mechanisms for resolvingmultiple patterning conflicts.

Optical lithography is a crucial step in semiconductor manufacturing.The basic principle of optical lithography is quite similar to that ofchemistry-based photography. The images of the patterned photo-mask areprojected through the high-precision optical system onto the wafersurface, which is coated with a layer of light-sensitive chemicalcompound, e.g. photo-resist. The patterns are then formed on the wafersurface after complex chemical reactions and follow-on manufacturingsteps, such as development, post-exposure bake, and wet or dry etching.

Multiple patterning is a class of technologies developed forphotolithography to enhance the feature density. The simplest case ofmultiple patterning is double patterning, where a conventionallithography process is enhanced to produce double the expected number offeatures. Double exposure is a sequence of two separate exposures of thesame photoresist layer using two different photomasks. This technique iscommonly used for patterns in the same layer which look very differentor have incompatible densities or pitches. In one important case, thetwo exposures may each consist of lines which are oriented in one or theother of two usually perpendicular directions. This allows thedecomposition of two-dimensional patterns into two one-dimensionalpatterns which are easier to print.

Double pattern lithography (DPL) is an effective technique to improveresolution. DPL theoretically doubles resolution through pitchsplitting. DPL involves two separate exposure and etch/freeze steps(litho-etch-litho-etch or litho-freeze-litho-etch). DPL is expected tobe needed for 20 nm technology and is one of the best candidatesolutions for scaling to 14 nm technology and beyond.

Layout decomposition includes mask assignment, also referred to as graphcoloring. In one case, shapes to be formed using photolithography arecolored such that two shapes within a predetermined distance are coloreddifferently, meaning they are formed using different photographic masks.Shapes of different masks can overlap. The point at which masks overlapis referred to as a stitch. Stitching is used to resolve a coloringconflict; however, not all conflicts can be resolved by stitching. Someconflicts require layout perturbation or modifications.

In one prior art solution, one may construct a conflict graph, detectodd cycles, and perform wire perturbation. One may repeat this processiteratively until no improvements are possible. Wire perturbationcomprises finding all possible perturbations to resolve a conflict andperform trial compaction. This solution has a very long runtime. Also,using this solution, it is impossible to cover all combinations ofperturbation. This solution does not consider impact on cross layerconstraints like via coverage, etc. A resolution of one conflict mayintroduce other conflicts. In addition, this solution only works with asingle spacing rule and cannot be used with shape-dependent designrules.

In another prior art solution, one may pre-compute all wire-spacingoptions that reduces conflicts. This solution formulates coloringproblem as integer linear programming (ILP) to minimize candidatewire-spreading options. This solution is very slow. This solution islimited to wire-spreading, and spreading may cause new conflicts atother places.

Another solution uses split level design for double pattern lithography.The solution specifies a DPL layer as two layers. For example, a metallayer, M1, is specified to the designer as M1 a and M1 b correspondingto two exposures of DPL. The designer must then consider inter- andintra-level ground rules to ensure DPL compatibility during design. Thissolution exposes the designer to DPL such that the designer must ensurethe design satisfies extra design rules for DPL compatibility.

The prior art solutions present trade-offs between“correct-by-construction” and “layout legalization” approaches.Correct-by-construction exposes designers to DPL complexity. Layoutlegalization flows are runtime intensive and suffer from the issue thatresolution of one conflict may create other conflicts. A conflictremoval flow should shield designers from DPL complexity and provideefficient flow that detects and fixes conflicts once and for allsimultaneously across all layers.

SUMMARY

In one illustrative embodiment, a method, in a data processing system,is provided for multiple patterning conflict resolution. The methodcomprises receiving a design layout for an integrated circuit andperforming decomposition to form a first mask and a second mask with allpossible stitch locations. The first mask and the second mask havecoloring conflicts such that at least one shape in the first mask or thesecond mask is too close to another shape in the same mask. The methodfurther comprises defining interactions between the first mask and thesecond mask using a set of split level design rules and fixing nativeconflicts in the first mask and the second mask by modifying at leastone shape in the first mask or the second mask subject to the set ofsplit level design rules to form a final layout.

In other illustrative embodiments, a computer program product comprisinga computer useable or readable medium having a computer readable programis provided. The computer readable program, when executed on a computingdevice, causes the computing device to perform various ones of, andcombinations of, the operations outlined above with regard to the methodillustrative embodiment.

In yet another illustrative embodiment, a system/apparatus is provided.The system/apparatus may comprise one or more processors and a memorycoupled to the one or more processors. The memory may compriseinstructions which, when executed by the one or more processors, causethe one or more processors to perform various ones of, and combinationsof, the operations outlined above with regard to the method illustrativeembodiment.

These and other features and advantages of the present invention will bedescribed in, or will become apparent to those of ordinary skill in theart in view of, the following detailed description of the exampleembodiments of the present invention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention, as well as a preferred mode of use and further objectivesand advantages thereof, will best be understood by reference to thefollowing detailed description of illustrative embodiments when read inconjunction with the accompanying drawings, wherein:

FIG. 1 is a diagram illustrating an example layout of wires to be formedusing photolithography with which aspects of the illustrativeembodiments may be implemented;

FIGS. 2A and 2B illustrate an example design with stitching and nativeconflicts for which aspects of the illustrative embodiments may beimplemented;

FIG. 3 illustrates finding a stitch location in accordance with theillustrative embodiment;

FIGS. 4A and 4B illustrate correction of native coloring conflicts inaccordance with an example embodiment;

FIGS. 5A and 5B illustrate correction of native coloring conflicts withthe same area in accordance with an example embodiment;

FIGS. 6A-6C illustrate another example of correction of native coloringconflicts in accordance with an example embodiment;

FIGS. 7A and 7B illustrate correction of native coloring conflicts inaccordance with an example embodiment;

FIG. 8 is a flowchart illustrating overall conflict resolution flow inaccordance with an illustrated embodiment;

FIG. 9 is a flowchart illustrating operation of a mechanism forperforming decomposition with all possible stitch locations inaccordance with an illustrative embodiment; and

FIG. 10 is a block diagram of an example data processing system in whichaspects of the illustrative embodiments may be implemented.

DETAILED DESCRIPTION

The illustrative embodiments provide a mechanism for resolvingpatterning conflicts. The mechanism performs decomposition with stitchesat all candidate locations to find the solution with the minimum numberof conflicts. The method works with any initial decomposition, e.g.,coloring, solution. The mechanism then defines interactions between thelayout of a first mask and a layout of a second mask through designrules. The mechanism then gives the decomposed layout and design ruledefinition to any existing design rule fixing or layout compaction toolto solve native conflicts. The modified design rules are that same-layerspacing equals spacing of single patterning, different-layer spacingequals spacing of final layout, and layer overlap equals minimum overlaplength.

FIG. 1 is a diagram illustrating an example layout of wires to be formedusing photolithography with which aspects of the illustrativeembodiments may be implemented. Layout 100 comprises a plurality of twodimensional shapes of wires to be formed using double patternlithography. As seen in FIG. 1, shape 102 is formed using a first mask(first color) and shape 104 is formed using a second mask (secondcolor). In this example, according to the goal of the embodimentsdescribed herein, all shapes can be formed using two photolithographicmasks. No two shapes of the same color are within a predetermineddistance of one another. As seen in this example, shape 106 is formedusing both the first mask and the second mask with a stitch where themasks overlap.

Mask assignment may be referred to as a “graph coloring problem,”meaning the problem of coloring the shapes such that no two shapes ofthe same color are within a predetermined distance of one another.Stitching may be used to resolve a coloring conflict. However, not allconflicts can be resolved by stitching.

FIGS. 2A and 2B illustrate an example design with stitching and nativeconflicts for which aspects of the illustrative embodiments may beimplemented. As seen in FIG. 2A, shapes 202, 204, 206, and 208 are tooclose to each other, referred to as native conflicts. FIG. 2Billustrates a solution with double pattern lithography. As seen in FIG.2B, shape 202 and shape 206 are colored differently, thus resolving theconflict. Also, shape 208 is formed using two different masks with astitch, thus resolving conflicts between shapes 206 and 208 and betweenshapes 208 and 210.

However, as shown in FIG. 2B, the conflict between shapes 204 and 206cannot be resolved. No matter how shapes 202, 204, and 206 are colored,there will always be an unresolved conflict with double patternlithography (DPL).

In accordance with the illustrative embodiments described herein, amechanism is provided that uses split level design rules to fix nativeconflicts simultaneously across multiple layers without creating newconflicts. The mechanism allows designers to design the original layoutwith conventional design rules, thus shielding the designer from DPLcomplexity.

The mechanism uses linear programming formulation for conflictresolution with minimum layout perturbation. The mechanism generates aninitial decomposition solution for DPL layers. The mechanism models thelayout as a constraint graph. A vertex represents an edge in the layout,and arcs represent decomposition and ground rule constraints betweenlayout edges. The mechanism treats DPL layers as stand-alonesingle-patterning layers.

The mechanism attempts to fix conflicts “once for all” with minimumperturbation while maintaining all inter- and intra-level connectivity,which may be represented as follows:

Minimize

${\sum\limits_{V_{i} \in V}\;{{{\hat{L}}_{i} - L_{i}}}},$

where L are drawn locations of layout edges and {circumflex over (L)}are modified locations of layout edges,

subject to:{circumflex over (L)} _(i) −{circumflex over (L)} _(j) ≧S _(ij) ∀A _(ij)∈A,

which represents the DPL split level and ground rule constraints.

The mechanism performs decomposition with all possible stitch locations.This decomposition must have a minimum number of native conflicts. Themechanism can be used with any initial decomposition solution but it isbetter to start with the minimum number of native conflicts if possible.The mechanism performs decomposition by finding all possible stitchlocations, assigning conflicting parts to the first and second masks,and reconstructing parts to the first and second mask. The mechanismfinds all possible stitch location by performing design rule dependentprojection, finding regions that do not conflict with any other feature,and stitching at non-conflicting parts that separate two conflictingparts. The mechanism assigns the conflicting parts to the first andsecond masks with a first objective of minimizing conflicts and a secondobjective of minimizing the number of stitches by trying to assign thetwo sides of a stitch to the same mask. The mechanism reconstructs byperforming mask assignment of non-conflicting parts. Any existingdecomposition flows that minimize native conflicts may also be used.

FIG. 3 illustrates finding a stitch location in accordance with theillustrative embodiment. The minimum size is the minimum size anisolated feature must have to be printable. The values t-s and t-trepresent the line-end (a.k.a. tip) to line-side minimum spacingrequirement and the line-end to line-side spacing requirement that thelayout must obey to be printable.

The mechanism then defines interactions between the layout of the firstmask and the layout of the second mask through split level design rules.The mechanism marks redundancy and extra input/output pads to possiblysacrifice them to resolve conflicts.

The mechanism then fixes native conflicts by modifying layout subject tosplit level design rules. This can be achieved by giving decomposedlayout and split level design rule definitions to an automated designrule fixing or layout migration tool. The modified split design rulescomprise a rule stating that same-layer spacing equals spacing of singlepatterning, a rule stating that different-layer spacing equals spacingof final layout, a rule stating that layer overlap equals a minimumoverlap length, and recommended rules for sacrificial parts.

FIGS. 4A and 4B illustrate correction of native coloring conflicts inaccordance with an example embodiment. FIG. 4A shows an original layout.As seen in FIG. 4A, the layout includes features with a native conflictthat cannot be resolved with a stitch. In accordance with theillustrative embodiment, a mechanism fixes native conflicts by modifyingthe layout subject to split level design rules. In this case, as shownin FIG. 4B, the mechanism shifts one or more shapes in the design to fixthe conflict with minimum perturbation. That is, the mechanism modifiesthe layout subject to the split level design rules while making thefewest modifications possible.

FIGS. 5A and 5B illustrate correction of native coloring conflicts withthe same area in accordance with an example embodiment. FIG. 5A shows anoriginal layout. As seen in FIG. 5A, the layout includes features with anative conflict that cannot be resolved with a stitch. In accordancewith the illustrative embodiment, a mechanism fixes native conflicts bymodifying the layout subject to split level design rules. In this case,as shown in FIG. 5B, the mechanism modifies one or more shapes in thedesign to fix the conflict such that the modified design uses the samearea.

FIGS. 6A-6C illustrate another example of correction of native coloringconflicts in accordance with an example embodiment. FIG. 6A shows anoriginal layout having four coloring conflicts. In accordance with theillustrative embodiment, a mechanism attempts to fix the conflicts bymodifying the layout subject to split level design rules. In this case,however, as shown in FIG. 6B, the mechanism is able to fix three of thefour conflicts using the same design area. As seen in FIG. 6C, themechanism is then able to fix the remaining conflict with an areaincrease. In accordance with the illustrative embodiments, the mechanismattempts to fix the remaining conflict subject to split level designrules with the minimum possible area increase.

FIGS. 7A and 7B illustrate correction of native coloring conflicts inaccordance with an example embodiment. FIG. 7A shows an original layouthaving coloring conflicts. FIG. 7B shows a final layout with conflictsresolved with increased area and removal of redundant I/O pads.

As will be appreciated by one skilled in the art, the present inventionmay be embodied as a system, method, or computer program product.Accordingly, aspects of the present invention may take the form of anentirely hardware embodiment, an entirely software embodiment (includingfirmware, resident software, micro-code, etc.) or an embodimentcombining software and hardware aspects that may all generally bereferred to herein as a “circuit,” “module” or “system.” Furthermore,aspects of the present invention may take the form of a computer programproduct embodied in any one or more computer readable medium(s) havingcomputer usable program code embodied thereon.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readable signalmedium or a computer readable storage medium. A computer readablestorage medium may be, for example, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, or semiconductor system,apparatus, device, or any suitable combination of the foregoing. Morespecific examples (a non-exhaustive list) of the computer readablestorage medium would include the following: an electrical connectionhaving one or more wires, a portable computer diskette, a hard disk, arandom access memory (RAM), a read-only memory (ROM), an erasableprogrammable read-only memory (EPROM or Flash memory), an optical fiber,a portable compact disc read-only memory (CDROM), an optical storagedevice, a magnetic storage device, or any suitable combination of theforegoing. In the context of this document, a computer readable storagemedium may be any tangible medium that can contain or store a programfor use by or in connection with an instruction execution system,apparatus, or device.

A computer readable signal medium may include a propagated data signalwith computer readable program code embodied therein, for example, in abaseband or as part of a carrier wave. Such a propagated signal may takeany of a variety of forms, including, but not limited to,electro-magnetic, optical, or any suitable combination thereof. Acomputer readable signal medium may be any computer readable medium thatis not a computer readable storage medium and that can communicate,propagate, or transport a program for use by or in connection with aninstruction execution system, apparatus, or device.

Computer code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, radio frequency (RF), etc., or anysuitable combination thereof.

Computer program code for carrying out operations for aspects of thepresent invention may be written in any combination of one or moreprogramming languages, including an object oriented programming languagesuch as Java™, Smalltalk™, C++, or the like, and conventional proceduralprogramming languages, such as the “C” programming language or similarprogramming languages. The program code may execute entirely on theuser's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer, or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

Aspects of the present invention are described below with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to the illustrativeembodiments of the invention. It will be understood that each block ofthe flowchart illustrations and/or block diagrams, and combinations ofblocks in the flowchart illustrations and/or block diagrams, can beimplemented by computer program instructions. These computer programinstructions may be provided to a processor of a general purposecomputer, special purpose computer, or other programmable dataprocessing apparatus to produce a machine, such that the instructions,which execute via the processor of the computer or other programmabledata processing apparatus, create means for implementing thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

These computer program instructions may also be stored in a computerreadable medium that can direct a computer, other programmable dataprocessing apparatus, or other devices to function in a particularmanner, such that the instructions stored in the computer readablemedium produce an article of manufacture including instructions thatimplement the function/act specified in the flowchart and/or blockdiagram block or blocks.

The computer program instructions may also be loaded onto a computer,other programmable data processing apparatus, or other devices to causea series of operational steps to be performed on the computer, otherprogrammable apparatus, or other devices to produce a computerimplemented process such that the instructions which execute on thecomputer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

FIG. 8 is a flowchart illustrating overall conflict resolution flow inaccordance with an illustrated embodiment. Operation begins, and aconflict resolution mechanism performs decomposition with all possiblestitch locations (block 802). The mechanism then defines interactionsbetween the layout of a first mask and the layout of a second maskthrough split level design rules (block 804), as well as interactions ofmask1/mask2 with top and bottom layers (i.e, contacts, vial, etc.). Aspart of defining interactions between the first mask and the secondmask, the mechanism may mark redundancy and extra I/O pads to possiblysacrifice them to resolve conflicts.

Then, the mechanism fixes native conflicts by modifying the layoutsubject to the split level design rules (block 806). The mechanism maybe achieved by giving decomposed layout and split level design ruledefinition to an automated design rule fixing or layout migration tool.The modified split design rules comprise a rule stating that same-layerspacing equals spacing of single patterning, a rule stating thatdifferent-layer spacing equals spacing of final layout, a rule statingthat layer overlap equals a minimum overlap length, and recommendedrules for sacrificial parts. Thereafter, operation ends.

FIG. 9 is a flowchart illustrating operation of a mechanism forperforming decomposition with all possible stitch locations inaccordance with an illustrative embodiment. Operation begins, and themechanism finds all possible stitch locations (block 902). The mechanismmay find all possible stitch locations by performing design ruledependent projections, finding regions that do not conflict with otherfeatures, and stitching at non-conflicting parts that separate twoconflicting parts. The mechanism then assigns conflicting parts to thefirst mask and the second mask (block 904). The mechanism may assignconflicting parts with the objectives of minimizing conflicts andminimizing the number of stitches by trying to assign the two sides of astitch to the same mask. Then, the mechanism reconstructs final layoutsof the two masks (block 906). The mechanism may mask assignment ofnon-conflicting parts in the final layouts of the two masks. Thereafter,the operation ends. Any existing decomposition flows that preferablyminimize conflicts that minimize native conflicts may also be used.

The flowchart and block diagrams in the figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

The illustrative embodiments may be utilized in many different types ofdata processing environments including a distributed data processingenvironment, a single data processing device, or the like. In order toprovide a context for the description of the specific elements andfunctionality of the illustrative embodiments, FIG. 10 is providedhereafter as an example environment in which aspects of the illustrativeembodiments may be implemented. It should be appreciated that FIG. 10 isonly an example and is not intended to assert or imply any limitationwith regard to the environments in which aspects or embodiments of thepresent invention may be implemented. Many modifications to the depictedenvironment may be made without departing from the spirit and scope ofthe present invention.

FIG. 10 is a block diagram of an example data processing system in whichaspects of the illustrative embodiments may be implemented. Dataprocessing system 1000 is an example of a computer in which computerusable code or instructions implementing the processes for illustrativeembodiments of the present invention may be located.

In the depicted example, data processing system 1000 employs a hubarchitecture including north bridge and memory controller hub (NB/MCH)1002 and south bridge and input/output (I/O) controller hub (SB/ICH)1004. Processing unit 1006, main memory 1008, and graphics processor1010 are connected to NB/MCH 1002. Graphics processor 1010 may beconnected to NB/MCH 1002 through an accelerated graphics port (AGP).

In the depicted example, local area network (LAN) adapter 1012 connectsto SB/ICH 1004. Audio adapter 1016, keyboard and mouse adapter 1020,modem 1022, read only memory (ROM) 1024, hard disk drive (HDD) 1026,CD-ROM drive 1030, universal serial bus (USB) ports and othercommunication ports 1032, and PCI/PCIe devices 1034 connect to SB/ICH1004 through bus 1038 and bus 1040. PCI/PCIe devices may include, forexample, Ethernet adapters, add-in cards, and PC cards for notebookcomputers. PCI uses a card bus controller, while PCIe does not. ROM 1024may be, for example, a flash basic input/output system (BIOS).

HDD 1026 and CD-ROM drive 1030 connect to SB/ICH 1004 through bus 1040.HDD 1026 and CD-ROM drive 1030 may use, for example, an integrated driveelectronics (IDE) or serial advanced technology attachment (SATA)interface. Super I/O(SIO) device 1036 may be connected to SB/ICH 1004.

An operating system runs on processing unit 1006. The operating systemcoordinates and provides control of various components within the dataprocessing system 1000 in FIG. 10. As a client, the operating system maybe a commercially available operating system such as Microsoft Windows 7(Microsoft and Windows are trademarks of Microsoft Corporation in theUnited States, other countries, or both). An object-oriented programmingsystem, such as the Java programming system, may run in conjunction withthe operating system and provides calls to the operating system fromJava programs or applications executing on data processing system 1000(Java is a trademark of Oracle and/or its affiliates.).

As a server, data processing system 1000 may be, for example, an IBM®eServer™ System p® computer system, running the Advanced InteractiveExecutive (AIX®) operating system or the LINUX operating system (IBM,eServer, System p, and AIX are trademarks of International BusinessMachines Corporation in the United States, other countries, or both, andLINUX is a registered trademark of Linus Torvalds in the United States,other countries, or both). Data processing system 1000 may be asymmetric multiprocessor (SMP) system including a plurality ofprocessors in processing unit 1006. Alternatively, a single processorsystem may be employed.

Instructions for the operating system, the object-oriented programmingsystem, and applications or programs are located on storage devices,such as HDD 1026, and may be loaded into main memory 1008 for executionby processing unit 1006. The processes for illustrative embodiments ofthe present invention may be performed by processing unit 1006 usingcomputer usable program code, which may be located in a memory such as,for example, main memory 1008, ROM 1024, or in one or more peripheraldevices 1026 and 1030, for example.

A bus system, such as bus 1038 or bus 1040 as shown in FIG. 10, may becomprised of one or more buses. Of course, the bus system may beimplemented using any type of communication fabric or architecture thatprovides for a transfer of data between different components or devicesattached to the fabric or architecture. A communication unit, such asmodem 1022 or network adapter 1012 of FIG. 10, may include one or moredevices used to transmit and receive data. A memory may be, for example,main memory 1008, ROM 1024, or a cache such as found in NB/MCH 1002 inFIG. 10.

Those of ordinary skill in the art will appreciate that the hardware inFIG. 10 may vary depending on the implementation. Other internalhardware or peripheral devices, such as flash memory, equivalentnon-volatile memory, or optical disk drives and the like, may be used inaddition to or in place of the hardware depicted in FIG. 10. Also, theprocesses of the illustrative embodiments may be applied to amultiprocessor data processing system, other than the SMP systemmentioned previously, without departing from the spirit and scope of thepresent invention.

Moreover, the data processing system 1000 may take the form of any of anumber of different data processing systems including client computingdevices, server computing devices, a tablet computer, laptop computer,telephone or other communication device, a personal digital assistant(PDA), or the like. In some illustrative examples, data processingsystem 1000 may be a portable computing device which is configured withflash memory to provide non-volatile memory for storing operating systemfiles and/or user-generated data, for example. Essentially, dataprocessing system 1000 may be any known or later developed dataprocessing system without architectural limitation.

Thus, the illustrative embodiments provide mechanisms for resolvingpatterning conflicts. The mechanism performs decomposition with stitchesat all candidate locations to find the solution with the minimum numberof conflicts. The mechanism then defines interactions between the layoutof a first mask and a layout of a second mask through design rules. Themechanism then gives the decomposed layout and design rule definition toany existing design rule fixing or layout compaction tool to solvenative conflicts. The modified design rules are that same-layer spacingequals spacing of single patterning, different-layer spacing equalsspacing of final layout, and layer overlap equals minimum overlaplength.

The illustrative embodiments provide a non-iterative double patterninglithography (DPL) conflict removal flow that simultaneously fixesconflicts once for all. The illustrative embodiments provide the abilityto sacrifice redundancy for conflict removal. The illustrativeembodiments also mask DPL complexity from designers. The mechanism ofthe illustrative embodiments provides full computer aided design (CAD)flow for enablement of double patterning needed at 20 nm and beyond. Theillustrative embodiments address a key need for double patterningenablement while maintaining design efficiency and designerproductivity. In addition, the illustrative embodiments may exploitexisting layout migration tools to enable automated conflict removal.

As noted above, it should be appreciated that the illustrativeembodiments may take the form of an entirety hardware embodiment, anentirely software embodiment or an embodiment containing both hardwareand software elements. In one example embodiment, the mechanisms of theillustrative embodiments are implemented in software or program code,which includes but is not limited to firmware, resident software,microcode, etc.

A data processing system suitable for storing and/or executing programcode will include at least one processor coupled directly or indirectlyto memory elements through a system bus. The memory elements can includelocal memory employed during actual execution of the program code, bulkstorage, and cache memories which provide temporary storage of at leastsome program code in order to reduce the number of times code must beretrieved from bulk storage during execution.

Input/output or I/O devices (including but not limited to keyboards,displays, pointing devices, etc.) can be coupled to the system eitherdirectly or through intervening I/O controllers. Network adapters mayalso be coupled to the system to enable the data processing system tobecome coupled to other data processing systems or remote printers orstorage devices through intervening private or public networks. Modems,cable modems and Ethernet cards are just a few of the currentlyavailable types of network adapters.

The description of the present invention has been presented for purposesof illustration and description, and is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the art. Theembodiment was chosen and described in order to best explain theprinciples of the invention, the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

1. A method, in a data processing system, for multiple patterningconflict resolution, the method comprising: receiving, by the dataprocessing system, a design layout for an integrated circuit;performing, by the data processing system, decomposition to form atleast a first mask and a second mask with stitch locations, wherein thefirst mask and the second mask have coloring conflicts such that atleast one shape in the first mask or the second mask is too close toanother shape in the same mask; defining, by the data processing system,interactions between the first mask and the second mask using a set ofsplit level design rules, wherein the set of split level design rulescomprises a rule stating that same-layer spacing equals spacing ofsingle patterning, a rule stating that different-layer spacing equalsspacing of a final layout, a rule stating that layer overlap equals aminimum overlap length, and recommendation rules for sacrificial parts;and automatically fixing, by the data processing system, nativeconflicts in the first mask and the second mask by modifying at leastone shape in the first mask or the second mask subject to the set ofsplit level design rules to form the final layout.
 2. The method ofclaim 1, wherein performing decomposition comprises: finding allpossible stitch locations; assigning conflicting parts to the first maskand the second mask; and reconstructing final layouts of the first maskand the second mask.
 3. The method of claim 2, wherein finding allpossible stitch locations comprises: performing design rule dependentprojections; finding regions that do not conflict with any otherfeature; and stitching at non-conflicting parts that separate twoconflicting parts.
 4. The method of claim 2, wherein assigningconflicting parts to the first mask and the second mask comprisesassigning conflicting parts such that the final layouts of the firstmask and the second mask have a minimum number of conflicts.
 5. Themethod of claim 2, wherein assigning conflicting parts to the first maskand the second mask comprises assigning conflicting parts such that thefinal layouts of the first mask and the second mask have a minimumnumber of stitches by attempting to assign two sides of a given stitchto the same mask.
 6. The method of claim 1, wherein defininginteractions between the first mask and the second mask comprisesmarking redundancy and extra input/output pads for removal.
 7. Themethod of claim 1, wherein fixing native conflicts comprises providingthe decomposed layout and the set of split level design rules to anautomated design rule fixing or layout migration tool.
 8. A computerprogram product comprising a computer readable storage medium having acomputer readable program stored therein, wherein the computer readableprogram, when executed on a computing device, causes the computingdevice to: receive a design layout for an integrated circuit; performdecomposition to form at least a first mask and a second mask withstitch locations, wherein the first mask and the second mask havingcoloring conflicts such that at least one shape in the first mask or thesecond mask is too close to another shape in the same mask; defineinteractions between the first mask and the second mask using a set ofsplit level design rules, wherein the set of split level design rulescomprises a rule stating that same-layer spacing equals spacing ofsingle patterning, a rule stating that different-layer spacing equalsspacing of a final layout, a rule stating that layer overlap equals aminimum overlap length, and recommendation rules for sacrificial parts;and automatically fix native conflicts in the first mask and the secondmask by modifying at least one shape in the first mask or the secondmask subject to the set of split level design rules to form the finallayout.
 9. The computer program product of claim 8, wherein performingdecomposition comprises: finding all possible stitch locations;assigning conflicting parts to the first mask and the second mask; andreconstructing final layouts of the first mask and the second mask. 10.The computer program product of claim 9, wherein finding all possiblestitch locations comprises: performing design rule dependentprojections; finding regions that do not conflict with any otherfeature; and stitching at non-conflicting parts that separate twoconflicting parts.
 11. The computer program product of claim 9, whereinassigning conflicting parts to the first mask and the second maskcomprises assigning conflicting parts such that the final layouts of thefirst mask and the second mask have a minimum number of conflicts. 12.The computer program product of claim 9, wherein assigning conflictingparts of the first mask and the second mask comprises assigningconflicting parts such that the final layouts of the first mask and thesecond mask have a minimum number of stitches by attempting to assigntwo sides of a given stitch to the same mask.
 13. The computer programproduct of claim 8, wherein defining interactions between the first maskand the second mask comprises marking redundancy and extra input/outputpads for removal.
 14. The computer program product of claim 8, whereinfixing native conflicts comprises providing the decomposed layout andthe set of split level design rules to an automated design rule fixingor layout migration tool.
 15. The computer program product of claim 8,wherein the computer readable program is stored in a computer readablestorage medium in a data processing system and wherein the computerreadable program was downloaded over a network from a remote dataprocessing system.
 16. The computer program product of claim 8, whereinthe computer readable program is stored in a computer readable storagemedium in a server data processing system and wherein the computerreadable program is downloaded over a network to a remote dataprocessing system for use in a computer readable storage medium with theremote system.
 17. An apparatus, comprising: a processor; and a memorycoupled to the processor, wherein the memory comprises instructionswhich, when executed by the processor, cause the processor to: receive adesign layout for an integrated circuit; perform decomposition to format least a first mask and a second mask with stitch locations, whereinthe first mask and the second mask have coloring conflicts such that atleast one shape in the first mask or the second mask is too close toanother shape in the same mask; define interactions between the firstmask and the second mask using a set of split level design rules,wherein the set of split level design rules comprises a rule statingthat same-layer spacing equals spacing of single patterning, a rulestating that different-layer spacing equals spacing of a final layout, arule stating that layer overlap equals a minimum overlap length, andrecommendation rules for sacrificial parts; and automatically fix nativeconflicts in the first mask and the second mask by modifying at leastone shape in the first mask or the second mask subject to the set ofsplit level design rules to form the final layout.
 18. The apparatus ofclaim 17, wherein performing decomposition comprises: finding allpossible stitch locations; assigning conflicting parts to the first maskand the second mask; and reconstructing final layouts of the first maskand the second mask.
 19. The apparatus of claim 17, wherein defininginteractions between the first mask and the second mask comprisesmarking redundancy and extra input/output pads for removal.
 20. Theapparatus of claim 17, wherein fixing native conflicts comprisesproviding the decomposed layout and the set of split level design rulesto an automated design rule fixing or layout migration tool.